1. Technical Field
The present invention is directed generally to integrated circuit technology. More specifically, the present invention is directed to a method of automating chip power consumption estimation.
2. Description of Related Art
As is well known in the art, the more digital logic integrated in a chip, the more power the chip consumes. It is further well known that many important design issues and parameters are strongly dependent on the power dissipation of the chip. And, since only a limited amount of heat can be dissipated through a chip's package, it is imperative that power consumption of chips be taken into account during the design process.
To this end, many techniques have been developed to estimate power consumption of chip at the design stage. One such technique includes pre-generating estimated power consumption values of circuit blocks or macros and storing the values in a file. These macros may be used once or a plurality of times to design different chips. In any event, once a chip incorporating these macros is designed, its estimated power consumption may quickly be calculated. To do so, one needs only determine the different macros as well as the number of instances each macro is used in the chip. Once this is determined, the estimated value of the macros may be obtained from the file and added together to arrive at the estimated power consumption of the chip.
Presently, the above-described chip-level power estimation is performed manually. This can be quite a time-consuming and calculation-intensive endeavor. For example, a typical microprocessor may contain more than one thousand (1,000) unique macros and each macro may be used more than 20,000 times. Hence, to compute the power estimation of the chip, 1,000 different values have to be retrieved from the file and used each more than 20,000 times.
Further, the design of a chip may constantly be changing. For every change, a new power estimation may have to be calculated. Thus, the amount of work that may have to be performed in obtaining the power estimation of a chip during its design process may be staggering. And, as with any task performed manually, this power estimation calculation is prone to errors.
Thus, what is needed is an apparatus, system and method of automating chip power consumption estimation.